PDF Icon "Investigation of the Mechanism of Floating Node Assisted CMOS Latch-Up, " S-P. Sim, P. Guo, A. Kordesch, W.F. Chen, C-M. Liu, C.Y. Yang and K. Lee", Technical Proceedings of the 2001 International Conference on Modeling and Simulation of Microsystems MSM 2001, http://www.comppub.com/publications/MSM/2001/pdf/T66.09.pdf

PDF Icon "Analysis of the holding current in CMOS latch-up," H. Matino, IBM Journal of Reasearch, Volume 29, Number 6, Page 588 (1985) Nontopical Issue. http://www.research.ibm.com/journal/rd/296/ibmrd2906F.pdf


PDF Icon "Evaluation of Device Susceptibility for Substrate Current on Chip Level by Mixed Mode (Device and Circuit) Simulation,"S. Mettler, W. Reiner, W. Wilkening Robert Bosch GmbHReutlingen and P. Pfaeffli, ISE AG Zurich," www.iis.ee.ethz.ch/nwp/subsafe/d431_final.pdf

PDF Icon "Latch-Up,ESD,And Other Phenomena," TI application report, Eilhard Haseloff, may 2000, http://focus.ti.com/lit/an/slya014a/slya014a.pdf.

PDF Icon "Layout dependence of CMOS latchup," Roberto Menozzi e.a., IEEE transactions on el. dev. Vol. 35, Nr. 11, November 1988, http://ee.unipr.it/~roberto/00007402.pdf

PDF Icon "Latchup in Integrated Circuits from Energetic Protons,"A. H. Johnston, G. M. Swift, and L. D.EdmondsJet Propulsion LaboratoryCalifornia Institute of TechnologyPasadena, California, http://parts.jpl.nasa.gov/docs/Prot_LU-97.pdf