PDF Icon "CHARACTERIZATION, MODELING, AND DESIGN OF
ESD PROTECTION CIRCUITS," STEPHEN G. BEEBE, Stanford University, 1998

PDF Icon "A New Integrated Metal-Semiconductor Simulation Methodology
for On-Chip Electrostatic Discharge Protection Design Optimization," Haigang Feng, Ke Gong, and Albert Wang, Department of Electrical & Computer Engineering. Illinois Institute of Technology.

PDF Icon "Whole-Chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Submicron CMOS VLSI," Ming-Dou Ker, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 1, JANUARY 1999

PDF Icon "Characterization and Optimization of a Bipolar ESD-Device by Measurements and Simulations," A. D. Stricker, S. Mettler, H. Wolf, M. Mergens, W. Wilkening, H. Gieser, and W. Fichtner, Proceedings of the 20th EOS/ESD Symposium, Reno NV, USA, October 4-8, 1998.

PDF Icon "Application of an ESD-MOS Compact Model for IC Design,"M. Mergens, W. Wilkening, H. Wolf, and W. Fichtner, ESD Forum 1999, Munich, Germany, 1999.

PDF Icon "MODELING AND CHARACTERIZATION OF SUBSTRATE RESISTANCE FOR DEEP SUBMICRON ESD PROTECTION DEVICES," Thesis, XIN YI ZHANG AUGUST 2002, http://www-tcad.stanford.edu/tcad/pubs/theses/xyz.pdf